Our lab (CSDL) researches EDA to improve PPA using both heuristic methods and AI. Our interests span all steps of physical design, analog circuit optimization, standard cell generation, and design-technology co-optimization (DTCO). We also focus on prediction, optimization and generation using ML and RL for each step of physical design and design space optimization (DSO). Additionally, we actively participate in the ISPD contest and ICCAD contest, which are published annually by the International Symposium of Physical Design (ISPD) every summer and the International Conference of Computer-Aided Design (ICCAD) every winter, respectively. Our current research is categorized as below.

• Physical Design
• GPU accelerated Global Placement
  
• Row-constraint Placement
  
• 3D-IC partitioning and placement
  
• Blob placement
  
• Analog Circuit Optimization
• RL-based analog circuit optimization
  
• ML-based fast circuit simulation
  
• Design-Technology Co-Optimization
• Multi-source transfer learning for DTCO
  
• Standard Cell Generation
• SAT based STD cell generation
  
• ML-based Prediction and Optimization
• XAI-based routability prediction and optimization
  
• GNN-based routing congestion prediction and optimization
  
• Transformer-based parasitic extraction
  
• GNN-based static timing analysis
  
• ML-based Generation
• GAN-based dummy fill generation
  
• Transformer based dummy fill generation
  
• LLM-based RTL generation
  
• RL-based Optimization
• BEOL configuration pathfinding
  
• RL-legalizer
  
• Discrete gate sizing for timing and power optimization
  
• Design Space Optimization
• FPGA design space optimization