Conference
CAD & SoC Design Laboratory

Conference

Total 12건 1 페이지
1999~
12 False Contour Noise Reduction of Plasma Display Panel through Dynamic Codeword Selection J. W. Lee and Y. H. Kim The 20th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2005), Jeju, Korea , Jul. 4~7, 2005 , Vol. 1, pp. 137-138
11 Level Converting Flip-Flops for Multi-VDD Systems H.S. Park, B.H. Lee, and Y.H. Kim The 20th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2005), Jeju, Korea , Jul. 4~7, 2005 , Vol. 1, pp. 97-98
10 Clock-free MTCMOS Flip-flops with High Speed and Low Power B.H. Lee, Y.H. Kim, and K.O. Jeong International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC) 2004, Sendai/Matsushima, Miyagi-Pref, Japan , Jul. 6~8, 2004 , pp. {8C2L-4-1}-{8C2L-4-4}
9  [Best Student Paper] A Cell Selection Algorithm for Area Minimization T.H. Kim and Y.H. Kim 6th International Conference on VLSI and CAD , Oct. 26~27, 1999 , pp. 29-31
8 Critical Path Analysis Considering the Signal Transition Time S.Y. Han, K.H. Kim, and Y.H. Kim 6th International Conference on VLSI and CAD , Oct. 26~27, 1999 , pp. 37-40
7 Efficient Glitch Generation Estimation in Logic Systems M. S. Kim, Y. H. Noh, J.Y. Choi, and Y.H. Kim International Conference on VLSI and CAD , Oct. 13~15, 1997 , pp. 247-249
6 An Efficient Loop Handling Algorithm for Critical Path Analysis Y.S. Kwon, S.Y. Han, and Y.H. Kim International Conference on VLSI and CAD , 1991 , pp. 325-328
5 The Timing Verification of Synchronous Systems Considering the Types of Synchronization Elements M.S. Sim, Y.S. Kwon, Y.S. Shin, and Y.H. Kim International Conference on VLSI and CAD , 1991 , pp. 329-332
4 An Accurate Delay Modeling Techniques for Switch-Level Timing Verification S. Hwang, Y.H. Kim, and R. Newton Proc. of Design Automation Conference, ACM/IEEE , Jun. 1986 , pp. 227-233
3 Electrical-Logic Simulation Y.H. Kim, J.E. Kleckner, R. Saleh, and A.R. Newton Digest of International Conference on CAD, IEEE , Nov. 1984
2 Register-Transfer Level Power Modeling for the Efficient Power estimation of VLSI systems Jung Yun Choi and Young Hwan Kim Proceedings of IEEK CAD & VLSI Design Conference , May. 1999 , pp. 135 - 137
1 Timing Verification for Latch-controlled VLSI Synchronous Systems Tae Hoon Kim and Young Hwan Kim Proceedings of KITE CAD & VLSI Design Conference , May. 1996 , pp. 48-51
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