Conference
CAD & SoC Design Laboratory

Conference

Total 40건 1 페이지
2009~2000
40 Improving the Process Variation Tolerability of Flip-Flops for UDSM Circuit Design E. J. Hwang, W. Kim, and Y. H. Kim The 11th International Symposium on Quality Electronic Design (ISQED 2010), San Jose, CA, USA , Mar. 22~24, 2010 , pp. 812 - 817
39 Evaluation of the State-of-the Art Statistical Leakage Estimation Methods using the BSIM4 Transistor Model J.-W. Kim, W. Kim, and Y. H. Kim The 12th International Symposium on Integrated Circuits (ISIC-2009), Singapore , Dec. 14~16, 2009 , pp. 409 - 412
38 High-level Statistical Static Timing Analysis under Process Variation T. H. Kim, W. Kim, J. W. Kim, and Y. H. Kim The 12th International Symposium on Integrated Circuits (ISIC-2009), Singapore , Dec. 14~16, 2009 , pp. 421 - 424
37 Impact of Process Variation on Timing Characteristics of MTCMOS Flip-flops for Low-power Mobile Multimedia Applications E. J. Hwang, W. Kim, and Y. H. Kim The 12th International Symposium on Integrated Circuits (ISIC-2009), Singapore , Dec. 14~16, 2009 , pp. 332 - 335
36 Effect of Local Random Variation on Gate-Level Delay and Leakage Statistical Analysis J. H. Kim, W. Kim, and Y. H. Kim Asia Symposium on Quality Electronic Design(Asqed) 2009, Kuala Lumpur, Malaysia , Jul. 15~16, 2009 , pp. 255 - 258
35 Assessment of Using Statistical Leakage Estimation at the Macro Level for VLSI Designs J. H. Kim, W. Kim, and Y. H. Kim The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2009), Jeju, Korea , Jul. 5~8, 2009
34 Assessment of Using Statistical Leakage Estimation at the Macro Level for VLSI Designs J. H. Kim, W. Kim, and Y. H. Kim The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2009), Jeju, Korea , Jul. 5~8, 2009
33 Efficient Load Model of Resistive Mesh Structured Power Network J.-W. Kim, and Y. H. Kim The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2009), Jeju, Korea , Jul. 5~8, 2009
32 Full Search Block Matching Algorithm using Pattern-based Sub-sampling for Low Power Hardware Implementation S.-J. Kang, D.-G. Yoo, S.-K. Lee, and Y. H. Kim The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2009), Jeju, Korea , Jul. 5~8, 2009
31 Single Power-Supply Voltage Level Converter for Multi-VDD Systems J. Y. An, H. S. Park, and Y. H. Kim The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2009), Jeju, Korea , Jul. 5~8, 2009
30 Adaptive Sum of the Bilateral Absolute Difference for Motion Estimation Using Temporal Symmetry D. G. Yoo, S. J. Kang, S. K. Lee, and Y. H. Kim The SID International Symposium, Seminar, and Exhibition, Texan, USA , May. 31~Jun. 5, 2009 , pp. 1271-1274
29 Design and Implementation of Median Filter based Adaptive Motion Vector Smoothing for Motion Compensated Frame Rate Up-Conversion S. J. Kang, D. G. Yoo, S. K. Lee, and Y. H. Kim The 13th IEEE International Symposium on Consumer Electronics (ISCE 2009), Kyoto, Japan , May. 25~28, 2009 , pp. 745-748
28 Low Cost and Flexible Processor-Based Controller for Timing Signal Generation in PDP J. W. Lee, M. J. Park, and Y. H. Kim The 13th IEEE International Symposium on Consumer Electronics (ISCE 2009), Kyoto, Japan , May. 25~28, 2009 , pp. 692-695
27 Incremental Statistical Static Timing Analysis with Gate Timing Yield Emphasis J. W. Kim, W. Kim, H. S. Park, and Y. H. Kim 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2008), Macau, China , Nov. 30~Dec. 3, 2008
26 Hardware Implementation of Motion Estimation Using a Sub-sampled Block for Frame Rate Up-Conversion S. J. Kang, D. G. Yoo, S. K. Lee, and Y. H. Kim International SoC Design Conference (ISOCC) 2008, Busan, Korea , Nov. 24~25, 2008 , Vol. 2, pp. II-101-II-104
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