Conference
CAD & SoC Design Laboratory

Conference

Total 7건 1 페이지
2015
7 Balanced Current Source Model of the Three-input Combinational Logic Gate for Timing Analysis Kai Chen and Young Hwan Kim 11th Conference on PhD Research in Microelectronics and Electronics (IEEE PRIME 2015), Glasglow, UK , Jun. 29, 2015~Jul. 2, 2015
6 Image Segmentation using Linked Mean-Shift Vectors with Region Attribution Analysis Hanjoo Cho and Young Hwan Kim 11th Conference on PhD Research in Microelectronics and Electronics (IEEE PRIME 2015), Glasglow, UK , Jun. 29, 2015~Jul. 2, 2015 , pp. 188-191
5 Foreground-based Depth Map Generation for 2D-to-3D Conversion Ho Sub Lee, Sung In Cho, Gyu Jin Bae, Hi-Seok Kim, and Young Hwan Kim International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal , May. 24, 2015~May. 27, 2015 , pp. 1210-1213
4 Current Source Model of Combinational Logic Gates for Accurate Gate-level Circuit Analysis and Timing Analysis Kai Chen, Young Hwan Kim VLSI Design, Automation and Test (VLSI-DAT 2015), Hsinchu, Taiwan , Apr. 27, 2015~Apr. 29, 2015
3 Automatic Depth Map Generation from a Single Image Using Segment-Adaptive Depth Merging Sung In Cho, Kyoungrok Cho, and Young Hwan Kim International Conference on Consumer Electronics, Las Vegas, USA , Jan. 9, 2015~Jan. 12, 2015 , pp. 668-669
2 An Optimal Operating Point By Using Error Monitoring Circuits with An Error-Resilient Technique Jaemin Lee, Seungwon Kim, Youngmin Kim and Seokhyeong Kang Proc. IFIP/IEEE International Conference on Very Large Scale Integration , 2015 , pp.69-73
1 Novel Adaptive Power Gating Strategy of TSV-based Multi-layer 3D IC Seungwon Kim, Ki Jin Han, Seokhyeong Kang and Yougming Kim Proc. IEEE International Symposium on Quality Electronic Design , 2015 , pp. 537-541
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