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CAD & SoC Design Laboratory

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Conference

Total 3건 1 페이지

2018

3

Fast Chip-Package-PCB Coanalysis Methodology for Power Integrity of Multi-domain High-Speed Memory: A Case Study Seungwon Kim, Ki Jin Han, Youngmin Kim, and Seokhyeong Kang IEEE/ACM Design, Automation and Test in Europe Conference and Exhibition (DATE) , 2018

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2

Extract LUT Logics from a Downloaded Bitstream Data in FPGA Kyoungrok Cho, Minyoung Jeong, Eungu Jeong, and Younghwan Kim International Symposium on Circuits and Systems (ISCAS 2018), Firenze, Italy , May. 27, 2018~May. 30, 2018 , pp. 1-5

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1

An optimal gate design for the synthesis of ternary logic circuits Sunmean Kim, Taeho Lim and Seokhyeong Kang Proc. Asia and South Pacific Design Automation Conference , 2018 , pp. 476 – 481

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