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1 페이지
2019
4
Fence-Region-Aware Mixed-Height Standard Cell Legalization
SangGi Do, Mingyu Woo, and Seokhyeong Kang
ACM Great Lakes Symposium on VLSI (GLSVLSI)
Paper
LINK
3
Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic
Sunmean Kim, Sung-Yun Lee, Sunghye Park, and Seokhyeong Kang
IEEE International Symposium on Multiple-Valued Logic (ISMVL)
,
2019
Paper
LINK
2
Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm
Sung-Yun Lee, Sunmean Kim, and Seokhyeong Kang
IEEE International Symposium on Multiple-Valued Logic (ISMVL)
,
2019
Paper
LINK
1
Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology
Andrew B. Kahng, Seokhyeong Kang, Seungwon Kim, Kambiz Samadi and Bangqi Xu
Proc. Design, Automation and Test in Europe
,
2019
, to appear
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