Conference
CAD & SoC Design Laboratory

Conference

An optimal gate design for the synthesis of ternary logic circuits
Author Sunmean Kim, Taeho Lim and Seokhyeong Kang
Journal Proc. Asia and South Pacific Design Automation Conference
Impact factor pp. 476 – 481
Year 2018
Category
File 첨부 2018_ASP-DAC_SMK_Paper.pdf (1.7M) 2회 다운로드 DATE : 2025-08-04 21:09:14
Link 관련링크 https://www.researchgate.net/publication/323347527_An_optimal_gate_des… 158회 연결

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