| Optimizing Ternary Multiplier Design with Fast Ternary Adder | |
|---|---|
| Author | Jongho Yoon, Seunghan Baek, Sunmean Kim and Seokhyeong Kang |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Impact factor | |
| Year | 2023 |
| Category | |
| File |
Optimizing_Ternary_Multiplier_Design_with_Fast_Ternary_Adder.pdf
(1.5M)
123회 다운로드
DATE : 2022-10-25 17:40:02
|
| Link |
https://ieeexplore.ieee.org/document/9904877
1341회 연결
|
Publications
CAD & SoC Design Laboratory
CAD & SoC Design Laboratory
LG Engineering Building (302, 318), 77 Cheongam-Ro, Nam-Gu, Pohang, Gyeongbuk, Korea, 37673TEL : +82-54-279-2883 l E-mail : shkang@postech.ac.kr COPYRIGHT ⓒ2018 CSDL. ALL RIGHT RESERVED.