Projects
CAD & SoC Design Laboratory
Projects
| Hierarchical Power/Delay Estimation/Optimization Techniques for High-Speed/Low-Power Information Equipment Designs | |
|---|---|
| 연구기간 | 1997.07.01 - 2001.06.30 |
| 기관 | Hyundai Semiconductor |
| Hierarchical Power/Delay Estimation/Optimization Techniques for High-Speed/Low-Power Information Equipment Designs | |
|---|---|
| 연구기간 | 1997.07.01 - 2001.06.30 |
| 기관 | Hyundai Semiconductor |
CAD & SoC Design Laboratory
Science Building II (308, 402), 77 Cheongam-Ro. Nam-Gu. Pohang. Gyeongbuk. Korea 37673