Projects
CAD & SoC Design Laboratory
Projects
| Power Estimation Techniques for VLSI Designs at the Register Transfer Level (II) | |
|---|---|
| 연구기간 | 1998.03.01 - 1999.02.28 |
| 기관 | Samsung Electronics Co.,Ltd. |
| Power Estimation Techniques for VLSI Designs at the Register Transfer Level (II) | |
|---|---|
| 연구기간 | 1998.03.01 - 1999.02.28 |
| 기관 | Samsung Electronics Co.,Ltd. |
CAD & SoC Design Laboratory
Science Building II (308, 402), 77 Cheongam-Ro. Nam-Gu. Pohang. Gyeongbuk. Korea 37673