BS. from EE, POSTECH, Pohang (Mar. 2017 - Aug. 2021)
Research Area
VLSI CAD, Physical Design, AI-EDA
Conference Paper
J. Ahn, J. Cho, J. Seo, J. Lee, J. Lee and S. Kang, “A Heterogeneous Graph-based Gate Sizer Integrating Graph Attention Network and Transformer,” IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), 2026.
J. Cho, J. Im, J. Lee, K. Min, S. Park, J. Seo, J. Yoon and S. Kang, “Leveraging Machine Learning Techniques to Enhance Traditional EDA Workflows,” IEEE/ACM Asia and South Pacific Design Automation Conference (ASP‐DAC), 2025. (Invited Paper)
J. Seo, S. Park, J. Seo and S. Kang, “Post‐place Optimization Using Multi‐agent Reinforcement Learning,” International SoC Design Conference (ISOCC), 2024. (ISOCC 2024 Synopsys Award)
J. Seo, S. Park, and S. Kang, “Improving Timing & Power Trade‐off in Post‐place Optimization Using Multi‐agent Reinforcement Learning,” IEEE/ACM International Conference on Computer‐Aided Design (ICCAD), 2024.
J. Seo, S. Park, and S. Kang, “Unveiling the Black‐Box: Leveraging Explainable AI for FPGA Design Space Optimization,” IEEE/ACM Design, Automation and Test in Europe Conference & Exhibition (DATE), 2024.
J. Seo, K. Min and S. Kang, “SAT‐based Minimum Patch Generation for Functional ECO”, The 29th Korean Conference on Semiconductors (KCS), 2022.
Patents
강석형, 서재민, and 박세진, “다중 에이전트 강화학습을 활용하여 디지털회로 타이밍 및 전력을 동시에 결정하는 방법 및 장치,” 출원번호: 10‐2025‐0106678, 등록(공개)번호: (진행중) (2025)
Awards/Contests
4th POSTECH‐EE Excellent Research Performance Contest ‐ 2nd Prize
31st ACM International Symposium on Physical Design (ISPD 2022) Contest ‐ Honorable mention
2020 Summer SK Hynix Undergraduate Internship Best Intern Award ‐ 1st in CIS group