Current member
CAD & SoC Design Laboratory

Current member

Seonghyeon Park

MS-Ph.D. student at EE, POSTECH from 2021

  •   Tel : +82-54-279-5587
  •   Location : Science Building II 308, 77 Cheongam-Ro. Nam-Gu. Pohang. Gyeongbuk. Korea 37673
  •   Email : seonghyeon98@postech.ac.kr

Education

  • BS. from EE, POSTECH, Pohang (Mar. 2017 - Aug. 2021)

Conference Paper

  • Jinoh Cho, Jinmo Ahn, Jakang Lee, Jaeseung Lee, Seonghyeon Park and Seokhyeong Kang, “Differentiable Fill Insertion with Explicit Delay Optimization”, in ACM/IEEE Design Automation Conference (DAC), 2026.
  • Andrew B. Kahng, Seokhyeong Kang, Sayak Kundu, Yiting Liu, Davit Makarian, Seonghyeon Park and Zhiang Wang, “Invited: Post-Placement Buffering and Sizing Contest”, in ACM/IEEE Symposium on Physical Design (ISPD), 2026.
  • Hyeonwoo Park, Seonghyeon Park and Seokhyeong Kang, “Late Breaking Results: Fine‐Tuning LLMs for Test Stimuli Generation”, in ACM/IEEE Design Automation Conference (DAC), 2025.
  • JoonSeok Kim*, Donggyu Kim*, Seonghyeon Park and Seokhyeong Kang, “FedEDA: Federated Learning Framework for Privacy‐Preserving Machine Learning in EDA”, in ACM/IEEE Design Automation Conference (DAC), 2025.
  • Kyungjun Min*, Seonghyeon Park*, Hyeonwoo Park, Jinoh Cho and Seokhyeong Kang, “Improving LLM‐based Verilog Code Generation with Data Augmentation and RL”, in IEEE/ACM Design, Automation and Test in Europe Conference & Exhibition (DATE), 2025.
  • Jinoh Cho, Jaekyung Im, Jaeseung Lee, Kyungjun Min, Seonghyeon Park, Jaemin Seo, Jongho Yoon and Seokhyeong Kang, “Leveraging Machine Learning Techniques to Enhance Traditional EDA Workflows”, in IEEE/ACM Asia and South Pacific Design Automation Conference (ASP‐DAC), 2025.
  • Jinoh Cho, Seonghyeon Park, Jakang Lee, Sung‐Yun Lee, Jinmo Ahn and Seokhyeong Kang, “RL‐Fill: Timing‐Aware Fill Insertion Using Reinforcement Learning”, in IEEE/ACM International Conference on Computer‐Aided Design (ICCAD), 2024.
  • Andrew B. Kahng, Seokhyeong Kang, Sayak Kundu, Kyungjun Min, Seonghyeon Park and Bodhisatta Pramanik, “PPA‐Relevant Clustering‐Driven Placement for Large‐Scale VLSI Designs”, in ACM/IEEE Design Automation Conference (DAC), 2024.
  • Seonghyeon Park, Daeyeon Kim and Seokhyeong Kang, “Invited: Acceleration on Physical Design: Machine Learning‐based Routability Optimization”, in ACM/IEEE International Workshop on System‐Level Interconnect Prediction (SLIP), 2023.
  • Seonghyeon Park, Daeyeon Kim, Seongbin Kwon, and Seokhyeong Kang, “Routability Prediction and Optimization Using Explainable AI”, in IEEE/ACM International Conference on Computer‐Aided Design (ICCAD), 2023.
  • Jakang Lee, Jaeseung Lee, Seonghyeon Park and Seokhyeong Kang, “Multi‐Source Transfer Learning for Design Technology Co‐Optimization”, in IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2023.
  • Sung‐Yun Lee, Seonghyeon Park, Daeyeon Kim, Minjae Kim, Tuyen P. Le and Seokhyeong Kang, “RL‐Legalizer: Reinforcement Learning‐based Cell Priority Optimization in Mixed‐Height Standard Cell Legalization”, in IEEE/ACM Design, Automation and Test in Europe Conference & Exhibition (DATE), 2023.
  • Jaeseung Lee, Jakang Lee, Seonghyeon Park and Seokhyeong Kang, “MLB: Multi‐Vth Tuning for Leakage Power Reduction via Bayesian Optimization”, in 2023 30th Korean Conference on Semiconductors (KCS), 2023.
  • Seonghyeon Park, Sung‐Yun Lee and Seokhyeong Kang, “Reinforcement Learning Based Detailed Placement”, in 2022 29th Korean Conference on Semiconductors (KCS), 2022.

Patents

  • Seokhyeong Kang, Jakang Lee, Jaeseung Lee, Hyungock Kim, Seonghyeon Park, "Integrated circuit design system for performing dtco (design technology co-optimization)", US (International), 2025.
  • 강석형, 민경준, 박성현, 조진오, 박현우, "데이터 증강 및 강화학습을 활용하여 베릴로그 코드 생성을 위한 거대 언어 모델을 트레이닝하는 방법 및 장치", Korea (Domestic), 10-2025-0145410.
  • 강석형, 조진오, 박성현, 이자강, 이승윤, 안진모, "모방학습 및 강화학습 기반의 타이밍을 고려하여 집적 회로를 설계하는 방법 및 장치", Korea (Domestic), 10-2025-0145475.
  • 강석형,이자강,이재승,박성현, "설계 기술 공동 최적화를 위한 여러 소스 전이 학습 방법", Korea (Domestic), 10-2024-0065267.

Awards/Contests

  • Contest Organizer - ISPD26 Contest: Post-Placement Buffering and Sizing, 2026.
  • Best Poster Award - International SoC Deisgn Conference (ISOCC), 2024.
  • 2nd Prize in POSTECH‐EE Excellent Research Performance Constest Pohang, Korea - POSTECH, 2023.
  • Invited Talk - International Workshop on System‐Level Interconnect Pathfinding (SLIP), 2023.