Current member
CAD & SoC Design Laboratory

Current member

Jaeseung Lee

MS-Ph.D. student at EE, POSTECH from 2022

  •   Tel : +82-54-279-5587
  •   Location : Science Building II 402, 77 Cheongam-Ro. Nam-Gu. Pohang. Gyeongbuk. Korea 37673
  •   Email : jae2seung@postech.ac.kr

Education

  • BS. from CITE & CSE, POSTECH, Pohang (Mar. 2018 – Feb. 2022)

Research Area

  • AI-EDA, ML Based tool
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음성 기능은 200자로 제한됨
옵션 : 역사 : 닫기

Conference Paper

  • Jaeseung Lee, Sunggyu Jang, Jakang Lee, and Seokhyeong Kang, “ LIBMixer: An all‑MLP Architecture for Cell Library AUGUST 26, 2025 1 Characterization towards Design Space Optimization”, in IEEE/ACM Asia and South Pacific Design Automation Conference (ASP‑ DAC), 2025.
  • Jinoh Cho, Jaekyung Im, Jaeseung Lee, Kyungjun Min, Seonghyeon Park, Jaemin Seo, Jongho Yoon, and Seokhyeong Kang, "Leveraging Machine Learning Techniques for Traditional EDA Workflow Enhancement", in Asia and South Pacific Design Automation Conference (ASP-DAC), 2025
  • Jaeseung Lee, Sejin Park, Minhyeok Kwon, and Seokhyeong Kang, “ Machine Learning‑based Fast Circuit Simulation for Analog Circuit Array”, in ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD), 2023.
  • Jaeseung Lee, Jakang Lee, Seonghyeon Park, and Seokhyeong Kang, “Multi‑Source Transfer Learning based Design Technology Co‑Optimization Framework”, in 2024 31th Korean Conference on Semiconductors (KCS), 2024.
  • Jakang Lee, J​aeseung Lee, Seonghyeon Park, and Seokhyeong Kang, “Multi‑Source Transfer Learning for Design Tech‑ nology Co‑Optimization”, in IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2023
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음성 기능은 200자로 제한됨
옵션 : 역사 : 닫기

Patents

  • Seokhyeong Kang, Jakang Lee, Jaeseung Lee, Hyungock Kim, Seonghyeon Park, "INTEGRATED CIRCUIT DESIGN SYSTEM PERFORMING DTCO", Korea (Domestic), 2024
  • Seokhyeong Kang, Jaeseung Lee, Sunggyu Jang, Jakang Lee, "METHOD AND APPARATUS FOR CHARACTERIZING A STANDARD INTEGRATED CELL LIBRARY USING ARTIFICIAL INTELLIGENCE", Korea (Domestic), 2025