Alumni
CAD & SoC Design Laboratory
Alumni
Jakang Lee
Ph.D Student at VLSI CAD Lab., UCSD
Education
- MS. from EE, POSTECH, Pohang (Mar. 2021 - Feb. 2023)
CAD & SoC Design Laboratory
Science Building II (308, 402), 77 Cheongam-Ro. Nam-Gu. Pohang. Gyeongbuk. Korea 37673TEL : +82-54-279-5587 l E-mail : shkang@postech.ac.kr
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