Conference
CAD & SoC Design Laboratory

Conference

Total 190건 10 페이지
2010
55 Toward Effective Utilization of Timing Exceptions in Design Optimization Kwangok Jeong, Andrew B. Kahng and Seokhyeong Kang Proc. International Symposium on Quality Electronic Design , 2010 , pp. 54–61
54 Designing a Processor From the Ground Up to Allow Voltage/Reliability Tradeoffs Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar and John Sartori Proc. International Symposium on High-Performance Computer Architecture , 2010 , pp. 119–129
53 Slack Redistribution for Graceful Degradation Under Voltage Overscaling Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar and John Sartori Proc. IEEE Asia and South Pacific Design Automation Conference , 2010 , pp. 825–831
2009~2000
52 Improving the Process Variation Tolerability of Flip-Flops for UDSM Circuit Design E. J. Hwang, W. Kim, and Y. H. Kim The 11th International Symposium on Quality Electronic Design (ISQED 2010), San Jose, CA, USA , Mar. 22~24, 2010 , pp. 812 - 817
51 Evaluation of the State-of-the Art Statistical Leakage Estimation Methods using the BSIM4 Transistor Model J.-W. Kim, W. Kim, and Y. H. Kim The 12th International Symposium on Integrated Circuits (ISIC-2009), Singapore , Dec. 14~16, 2009 , pp. 409 - 412
50 High-level Statistical Static Timing Analysis under Process Variation T. H. Kim, W. Kim, J. W. Kim, and Y. H. Kim The 12th International Symposium on Integrated Circuits (ISIC-2009), Singapore , Dec. 14~16, 2009 , pp. 421 - 424
49 Impact of Process Variation on Timing Characteristics of MTCMOS Flip-flops for Low-power Mobile Multimedia Applications E. J. Hwang, W. Kim, and Y. H. Kim The 12th International Symposium on Integrated Circuits (ISIC-2009), Singapore , Dec. 14~16, 2009 , pp. 332 - 335
48 Effect of Local Random Variation on Gate-Level Delay and Leakage Statistical Analysis J. H. Kim, W. Kim, and Y. H. Kim Asia Symposium on Quality Electronic Design(Asqed) 2009, Kuala Lumpur, Malaysia , Jul. 15~16, 2009 , pp. 255 - 258
47 Assessment of Using Statistical Leakage Estimation at the Macro Level for VLSI Designs J. H. Kim, W. Kim, and Y. H. Kim The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2009), Jeju, Korea , Jul. 5~8, 2009
46 Assessment of Using Statistical Leakage Estimation at the Macro Level for VLSI Designs J. H. Kim, W. Kim, and Y. H. Kim The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2009), Jeju, Korea , Jul. 5~8, 2009
45 Efficient Load Model of Resistive Mesh Structured Power Network J.-W. Kim, and Y. H. Kim The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2009), Jeju, Korea , Jul. 5~8, 2009
44 Full Search Block Matching Algorithm using Pattern-based Sub-sampling for Low Power Hardware Implementation S.-J. Kang, D.-G. Yoo, S.-K. Lee, and Y. H. Kim The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2009), Jeju, Korea , Jul. 5~8, 2009
43 Single Power-Supply Voltage Level Converter for Multi-VDD Systems J. Y. An, H. S. Park, and Y. H. Kim The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2009), Jeju, Korea , Jul. 5~8, 2009
42 Adaptive Sum of the Bilateral Absolute Difference for Motion Estimation Using Temporal Symmetry D. G. Yoo, S. J. Kang, S. K. Lee, and Y. H. Kim The SID International Symposium, Seminar, and Exhibition, Texan, USA , May. 31~Jun. 5, 2009 , pp. 1271-1274
41 Design and Implementation of Median Filter based Adaptive Motion Vector Smoothing for Motion Compensated Frame Rate Up-Conversion S. J. Kang, D. G. Yoo, S. K. Lee, and Y. H. Kim The 13th IEEE International Symposium on Consumer Electronics (ISCE 2009), Kyoto, Japan , May. 25~28, 2009 , pp. 745-748
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