Conference
CAD & SoC Design Laboratory

Conference

Total 199건 10 페이지
2010
64 Global Backlight Dimming Method Using Two-sided Gray-level Conversion for LCD S. I. Cho, S.-J. Kang, and Y. H. Kim International Meeting on Information Display (IMID), Seoul, Korea , Oct. 11~15, 2010
63 Performance Comparison of Fast Bilateral Motion Estimation Algorithms for Frame Rate Up-Conversion D.-G. Yoo, S.-J. Kang, S. K. Lee, and Y. H. Kim International Meeting on Information Display (IMID), Seoul, Korea , Oct. 11~15, 2010
62 Effect of Gate-level Design Margin Relaxation on Overall Circuit Performance Metrics in VLSI Design J. H. Kim, Y. H. Kim Asia Symposium on Quality Electronic Design(Asqed) 2010, Penang, Malaysia , Aug. 3~4, 2010 , pp. 314-317
61 Efficient Reduction Technique of Resistive Mesh Structured Power Network J. -W. Kim, Y. H. Kim Asia Symposium on Quality Electronic Design(Asqed) 2010, Penang, Malaysia , Aug. 3~4, 2010 , pp. 351-355
60 Dynamic Clipping Ratio Determination for Global Backlight Dimming in LCD P. Lavole, S.-K. Lee, S.-J. Kang and Y. H. Kim IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France , May. 30, 2010~Jun. 2, 2010 , pp. 3256 - 3259
59 Low-Power LCDs Using an Image Integrity-Based Backlight-Dimming Algorithm S.-J. Kang, H. Ahn, H. Hong, E. Oh, I. Chung, and Y. H. Kim The SID International Symposium, Seminar, and Exhibition, Seattle, USA , May. 23~28, 2010 , pp. 1005-1008
58 Surface-Based Adaptive Incremental Subfield Coding Method for Plasma Display Panels M. J. Park, J. W. Lee, and Y. H. Kim The SID International Symposium, Seminar, and Exhibition, Seattle, USA , May. 23~28, 2010 , pp. 1576-1579
57 Worst-Case Timing Analysis in UDSM Era J. Y. Ahn, T. H. Kim, H. G. Yang and Y. H. Kim ECTI-CON 2010, Chiangmai, Thailand , May. 19~21, 2010 , pp. 376 - 379
56 Effective Luminance Compensation: Advanced Driving Method to Improve LCD Response Time S. K. Lee and Y. H. Kim 13th international display workshops, Otsu, Japa , Dec. 6~8, 2006
55 Recovery-Driven Design: A Power Minimization Methodology for Error-Tolerant Processor Modules Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar and John Sartori Proc. ACM/IEEE Design Automation Conference , 2010 , pp. 825–830
54 Toward Effective Utilization of Timing Exceptions in Design Optimization Kwangok Jeong, Andrew B. Kahng and Seokhyeong Kang Proc. International Symposium on Quality Electronic Design , 2010 , pp. 54–61
53 Designing a Processor From the Ground Up to Allow Voltage/Reliability Tradeoffs Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar and John Sartori Proc. International Symposium on High-Performance Computer Architecture , 2010 , pp. 119–129
52 Slack Redistribution for Graceful Degradation Under Voltage Overscaling Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar and John Sartori Proc. IEEE Asia and South Pacific Design Automation Conference , 2010 , pp. 825–831
2009~2000
51 Improving the Process Variation Tolerability of Flip-Flops for UDSM Circuit Design E. J. Hwang, W. Kim, and Y. H. Kim The 11th International Symposium on Quality Electronic Design (ISQED 2010), San Jose, CA, USA , Mar. 22~24, 2010 , pp. 812 - 817
50 Evaluation of the State-of-the Art Statistical Leakage Estimation Methods using the BSIM4 Transistor Model J.-W. Kim, W. Kim, and Y. H. Kim The 12th International Symposium on Integrated Circuits (ISIC-2009), Singapore , Dec. 14~16, 2009 , pp. 409 - 412
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