Conference
CAD & SoC Design Laboratory

Conference

Total 190건 5 페이지
2020
130 GRLC: Grid-based Run-length Compression for Energy-efficient CNN Accelerator Yoonho Park, Yesung Kang, Sunghoon Kim, Eunji Kwon, and Seokhyeong Kang IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) , 2020
129 Late Breaking Results: Reinforcement Learning-based Power Management Policy for Mobile Device Systems Eunji Kwon, Sodam Han, Yoonho Park, Young Hwan Kim, and Seokhyeong Kang ACM/IEEE Design Automation Conference (DAC) , 2020
128 Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction Kiyung Kim, Sunmean Kim, Yongsu Lee, Daeyeon Kim, So-Young Kim, Seokhyeong Kang, and Byoung Hun Lee IEEE International Symposium on Multiple-Valued Logic (ISMVL) , 2020
127 Analysis and Solution of CNN Accuracy Reduction over Channel Loop Tiling Yesung Kang, Yoonho Park, Sunghoon Kim, Eunji Kwon, Taeho Lim, Sangyun Oh, Mingyu Woo, and Seokhyeong Kang IEEE/ACM Design, Automation and Test in Europe Conference and Exhibition (DATE) , 2020
2019
126 Fence-Region-Aware Mixed-Height Standard Cell Legalization SangGi Do, Mingyu Woo, and Seokhyeong Kang ACM Great Lakes Symposium on VLSI (GLSVLSI)
125 Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic Sunmean Kim, Sung-Yun Lee, Sunghye Park, and Seokhyeong Kang IEEE International Symposium on Multiple-Valued Logic (ISMVL) , 2019
124 Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm Sung-Yun Lee, Sunmean Kim, and Seokhyeong Kang IEEE International Symposium on Multiple-Valued Logic (ISMVL) , 2019
123 Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology Andrew B. Kahng, Seokhyeong Kang, Seungwon Kim, Kambiz Samadi and Bangqi Xu Proc. Design, Automation and Test in Europe , 2019 , to appear
2018
122 Fast Chip-Package-PCB Coanalysis Methodology for Power Integrity of Multi-domain High-Speed Memory: A Case Study Seungwon Kim, Ki Jin Han, Youngmin Kim, and Seokhyeong Kang IEEE/ACM Design, Automation and Test in Europe Conference and Exhibition (DATE) , 2018
121 Extract LUT Logics from a Downloaded Bitstream Data in FPGA Kyoungrok Cho, Minyoung Jeong, Eungu Jeong, and Younghwan Kim International Symposium on Circuits and Systems (ISCAS 2018), Firenze, Italy , May. 27, 2018~May. 30, 2018 , pp. 1-5
120 An optimal gate design for the synthesis of ternary logic circuits Sunmean Kim, Taeho Lim and Seokhyeong Kang Proc. Asia and South Pacific Design Automation Conference , 2018 , pp. 476 – 481
2017
119 A Preliminary Analysis of Domain Coupling in Package Power Distribution Network Byoungjin Bae, Seungwon Kim, Youngmin Kim, Seokhyeong Kang, Il Joon Kim, Kwangseok Kim, Sunwon Kang and Ki Jin Han IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) , 2017
118 Census transform-based static caption detection for frame rate up-conversion Gyujin Bae, Suk-Ju Kang, and Young Hwan Kim Circuits and Systems (ISCAS), 2017 IEEE International Symposium on, Baltimore, USA , May. 28, 2017~May. 31, 2017
117 Utilization of relieved corners from multi-corner libraries in deterministic static timing analysis Hyun-jeong Kwon, Young Hwan Kim VLSI Design, Automation and Test (VLSI-DAT), 2017 International Symposium on, Hsinchu, Taiwan , Apr. 24, 2017~Apr. 27, 2017
116 GRASP based Metaheuristics for Layout Pattern Classification Mingyu Woo, Seungwon Kim and Seokhyeong Kang Proc. IEEE/ACM International Conference on Computer-Aided Design , 2017 , pp. 512-518
게시물 검색