| Current Source Model of Combinational Logic Gates for Accurate Gate-level Circuit Analysis and Timing Analysis | |
|---|---|
| Author | Kai Chen, Young Hwan Kim |
| Journal | VLSI Design, Automation and Test (VLSI-DAT 2015), Hsinchu, Taiwan |
| Impact factor | |
| Year | Apr. 27, 2015~Apr. 29, 2015 |
| Category | |
| Link |
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=71145…
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