Conference
CAD & SoC Design Laboratory

Conference

Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction
Author Kiyung Kim, Sunmean Kim, Yongsu Lee, Daeyeon Kim, So-Young Kim, Seokhyeong Kang, and Byoung Hun Lee
Journal IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Impact factor
Year 2020
Category
File 첨부 2020_ISMVL_KYKim_paper.pdf (1.4M) 7회 다운로드 DATE : 2025-07-31 18:54:00
Link 관련링크 https://ieeexplore.ieee.org/document/9308509 296회 연결

Our submission to DATE 2020, "Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction" authored by Kiyung Kim, Sunmean Kim, Yongsu Lee, Daeyeon Kim, So-Young Kim, Seokhyeong Kang, and Byoung Hun Lee has been accepted.