| Timing Verification for Latch-controlled VLSI Synchronous Systems | |
|---|---|
| Author | Tae Hoon Kim and Young Hwan Kim |
| Journal | Proceedings of KITE CAD & VLSI Design Conference |
| Impact factor | pp. 48-51 |
| Year | May. 1996 |
| Category | |
. |
|
Conference
CAD & SoC Design Laboratory
Conference
CAD & SoC Design Laboratory
Science Building II (308, 402), 77 Cheongam-Ro. Nam-Gu. Pohang. Gyeongbuk. Korea 37673TEL : +82-54-279-5587 l E-mail : shkang@postech.ac.kr
개인정보취급처리방침 COPYRIGHT ⓒ2018 CSDL. ALL RIGHT RESERVED.