Register-Transfer Level Power Modeling for the Efficient Power estimation of VLSI systems Author Jung Yun Choi and Young Hwan Kim Journal Proceedings of IEEK CAD & VLSI Design Conference Impact factor pp. 135 - 137 Year May. 1999 Category . 목록 이전글Adaptive Scanorder Algorithm for Optimized Switching of PDP Data Drivers 18.12.27 다음글Timing Verification for Latch-controlled VLSI Synchronous Systems 18.12.27