Electrical-Logic Simulation Author Y.H. Kim, J.E. Kleckner, R. Saleh, and A.R. Newton Journal Digest of International Conference on CAD, IEEE Impact factor Year Nov. 1984 Category . 검색 목록 이전글An Accurate Delay Modeling Techniques for Switch-Level Timing Verification 18.12.27 다음글Register-Transfer Level Power Modeling for the Efficient Power estimation of VLSI systems 18.12.27