| Register-Transfer Level Power Modeling for the Efficient Power estimation of VLSI systems | |
|---|---|
| Author | Jung Yun Choi and Young Hwan Kim |
| Journal | Proceedings of IEEK CAD & VLSI Design Conference |
| Impact factor | pp. 135 - 137 |
| Year | May. 1999 |
| Category | |
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- 이전글Electrical-Logic Simulation 18.12.27
- 다음글Timing Verification for Latch-controlled VLSI Synchronous Systems 18.12.27
