Effect of Gate-level Design Margin Relaxation on Overall Circuit Performance Metrics in VLSI Design > Conference | 포항공대 CSDL

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Effect of Gate-level Design Margin Relaxation on Overall Circuit Performance Metrics in VLSI Design
Author	J. H. Kim, Y. H. Kim
Journal	Asia Symposium on Quality Electronic Design(Asqed) 2010, Penang, Malaysia
Impact factor	pp. 314-317
Year	Aug. 3~4, 2010
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Link	http://ieeexplore.ieee.org/search/srchabstract.jsp?tp=&arnumb… 265회 연결
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