| An optimal gate design for the synthesis of ternary logic circuits | |
|---|---|
| Author | Sunmean Kim, Taeho Lim and Seokhyeong Kang |
| Journal | 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) |
| Impact factor | |
| Year | 2018 |
| Category | |
| Link |
https://www.researchgate.net/publication/323347527_An_optimal_gate_des…
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