Conference
CAD & SoC Design Laboratory

Conference

AESPA: Algorithm-Hardware Co-Designed Early-Termination and Sparsity-Aware Processing Architecture
Author DongHwan Yoon, JoonSeok Kim, and Seokhyeong Kang
Journal 32nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Impact factor accepted
Year 2027
Category

Our submission to ASP-DAC 2027, "AESPA: Algorithm-Hardware Co-Designed Early-Termination and Sparsity-Aware Processing Architecture" authored by DongHwan Yoon, JoonSeok Kim, and Seokhyeong Kang has been accepted.