Conference
CAD & SoC Design Laboratory

Conference

An optimal gate design for the synthesis of ternary logic circuits
Author Sunmean Kim, Taeho Lim and Seokhyeong Kang
Journal 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)
Impact factor
Year 2018
Category
File 첨부 PID5123919.pdf (1,005.8K) 0회 다운로드 DATE : 2026-08-02 19:14:15
File 첨부 [Final] MVL_ASPDAC.pdf (9.6M) 0회 다운로드 DATE : 2026-08-02 19:14:15
Link 관련링크 https://ieeexplore.ieee.org/document/8297369 474회 연결

Our submission to ASP-DAC 2028, "An optimal gate design for the synthesis of ternary logic circuits" authored by Sunmean Kim, Taeho Lim and Seokhyeong Kang has been accepted.