Journal
CAD & SoC Design Laboratory

Journal

A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits
Author Sunmean Kim, Sung-Yun Lee, Sunghyeon Park, Kyung Rok Kim, and Seokhyeong Kang
Journal IEEE Transactions on Circuits and Systems I (TCAS-I)
Impact factor
Year 2020
Category
File 첨부 A_Logic_Synthesis_Methodology_for_Low-Power_Ternary_Logic_Circuits.pdf (3.7M) 3회 다운로드 DATE : 2025-08-05 16:34:14
Link 관련링크 https://ieeexplore.ieee.org/document/9089220 230회 연결

Our submission to TCAS-I 2020, "A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits" authored by Sunmean Kim, Sung-Yun Lee, Sunghyeon Park, Kyung Rok Kim, and Seokhyeong Kang has been accepted.