Comparison of Circuit Reduction Techniques for Power Network Noise Analysis > Journal | 포항공대 CSDL

Journal

CAD & SoC Design Laboratory

PUBLICATIONS
- INTRODUCTION
- RESEARCH
- ADVISOR
- MEMBERS
- PUBLICATIONS
- CLASS
- NEWS
- PHOTOS
- LINKS
Journal

Journal

Comparison of Circuit Reduction Techniques for Power Network Noise Analysis
Author	J.-W. Kim and Y. H. Kim
Journal	Journal of Semiconductor Technology and Science(SCI-E)
Impact factor	Vol. 9, No. 4, pp. 216-224
Year	Dec. 2009
Category
Link	http://www.jsts.org/html/journal/journal_files/2009/12/Year2009Volume0… 185회 연결
.

목록

이전글Level Up/Down Converter with Single Power-Supply Voltage for Multi-VDD Systems 18.12.27
다음글Image Integrity-based Gray-Level Error Control for Low Power Liquid Crystal Displays 18.12.27