| New Gate Models for Gate-level Delay Calculation under Crosstalk Effects | |
|---|---|
| Author | T. I. Bae, J. W. Kim, and Y. H. Kim |
| Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| Impact factor | Vol. E91-A, No. 12, pp. 3488-3496 |
| Year | Dec. 2008 |
| Category | |
| Link |
http://adsabs.harvard.edu/abs/2008IEITF..91.3488B
180회 연결
|
. |
|
Journal
CAD & SoC Design Laboratory
Journal
CAD & SoC Design Laboratory
Science Building II (308, 402), 77 Cheongam-Ro. Nam-Gu. Pohang. Gyeongbuk. Korea 37673TEL : +82-54-279-5587 l E-mail : shkang@postech.ac.kr
개인정보취급처리방침 COPYRIGHT ⓒ2018 CSDL. ALL RIGHT RESERVED.