| Assessment of Using the Statistical Timing Analysis Software for the VLSI Design at the Macro Level | |
|---|---|
| Author | H. G. Yang, W. Kim, and Y. H. Kim |
| Journal | International SoC Design Conference (ISOCC) 2008, Busan, Korea |
| Impact factor | Vol. 2, pp. II-187-II-190 |
| Year | Nov. 24~25, 2008 |
| Category | |
| Link |
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4815715
265회 연결
|
. |
|
Domestic
CAD & SoC Design Laboratory
Domestic
CAD & SoC Design Laboratory
Science Building II (308, 402), 77 Cheongam-Ro. Nam-Gu. Pohang. Gyeongbuk. Korea 37673TEL : +82-54-279-5587 l E-mail : shkang@postech.ac.kr
개인정보취급처리방침 COPYRIGHT ⓒ2018 CSDL. ALL RIGHT RESERVED.