| Hybrid gate-level 누설 전류 모델의 gate library characterization에 적합한 error metric | |
|---|---|
| Author | 권현정,박해성,김진욱,김영환 |
| Journal | 대한전자공학회 SoC 설계 연구회, UNIST |
| Impact factor | |
| Year | May. 16, 2015 |
| Category | |
. |
|
Domestic
CAD & SoC Design Laboratory
Domestic
CAD & SoC Design Laboratory
Science Building II (308, 402), 77 Cheongam-Ro. Nam-Gu. Pohang. Gyeongbuk. Korea 37673TEL : +82-54-279-5587 l E-mail : shkang@postech.ac.kr
개인정보취급처리방침 COPYRIGHT ⓒ2018 CSDL. ALL RIGHT RESERVED.