| Mixed-Level Timing 검증기 개발 | |
|---|---|
| Author | 한상열, 김영환 |
| Journal | 과학기술처, 91 특정연구발표회 |
| Impact factor | |
| Year | Aug. 1992 |
| Category | |
. |
|
- 이전글Gate-level Timing Verifier의 개발 (II) 18.12.27
- 다음글16 bit x 16 bit 승산기의 설계 trade-offs 18.12.27
Domestic
CAD & SoC Design Laboratory
Domestic
CAD & SoC Design Laboratory
Science Building II (308, 402), 77 Cheongam-Ro. Nam-Gu. Pohang. Gyeongbuk. Korea 37673TEL : +82-54-279-5587 l E-mail : shkang@postech.ac.kr
개인정보취급처리방침 COPYRIGHT ⓒ2018 CSDL. ALL RIGHT RESERVED.