| VeriLogos: Automatic Verilog RTL Generation using Large Language Models | |
|---|---|
| Author | Kyungjun Min, Seonghyeon Park, Hyeonwoo Park*, Seokhyeong Kang |
| Journal | International SoC Design Conference (ISOCC) |
| Impact factor | |
| Year | 2024 |
| Category | Best Poster Award |
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