| Timing-Aware Transistor-level P&R을 위한 ILP-based Routing Hiearchy Partitioning | |
|---|---|
| Author | Namsung Kim, and Seokhyeong Kang |
| Journal | 반도체공학회 학술대회 |
| Impact factor | |
| Year | 2026 |
| Category | |
Domestic
CAD & SoC Design Laboratory
Domestic
CAD & SoC Design Laboratory
Science Building II (308, 402), 77 Cheongam-Ro. Nam-Gu. Pohang. Gyeongbuk. Korea 37673TEL : +82-54-279-5587 l E-mail : shkang@postech.ac.kr
개인정보취급처리방침 COPYRIGHT ⓒ2018 CSDL. ALL RIGHT RESERVED.