| Timing Modeling and Optimization of Ternary Logic Gates for Circuit-level Analysis | |
|---|---|
| Author | Minhyuk Kweon , Jeyeong Park , Seunghan Baek , Seokhyeong Kang , and Sunmean Kim |
| Journal | Asia-Pacific Conference on Circuits and Systems (APCCAS) |
| Impact factor | |
| Year | 2025 |
| Category | |
Domestic
CAD & SoC Design Laboratory
Domestic
CAD & SoC Design Laboratory
Science Building II (308, 402), 77 Cheongam-Ro. Nam-Gu. Pohang. Gyeongbuk. Korea 37673TEL : +82-54-279-5587 l E-mail : shkang@postech.ac.kr
개인정보취급처리방침 COPYRIGHT ⓒ2018 CSDL. ALL RIGHT RESERVED.