Laboratory news
CAD & SoC Design Laboratory

Laboratory news

Our submission to ISMVL 2019, "Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic", authored by Sunmean Kim has been accepted.

페이지 정보

작성자 최고관리자 댓글 0건 조회 522회 작성일 19-02-17 21:47

본문

Our submission to ISMVL 2019, "Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic", authored by Sunmean Kim, Sung-Yun Lee, Sunghye Park, and Seokhyeong Kang has been accepted.

댓글목록

등록된 댓글이 없습니다.