HOME
LOGIN
SITEMAP
CONTACT US
Facebook link
INTRODUCTION
CSDL
Contact us
RESEARCH
Topic & Info
Projects
ADVISOR
MEMBERS
Current member
Alumni
PUBLICATIONS
CLASS
NEWS
Laboratory news
Alumni News
BBS
PHOTOS
LINKS
Home
Login
Introduction
CSDL
Contact us
Research
Topic & Info
Projects
Advisor
Advisor
Members
Current member
Alumni
Publications
Publications
Class
Class
News
Laboratory news
Alumni News
BBS
Photos
Photos
Links
Links
Laboratory news
CAD & SoC Design Laboratory
NEWS
INTRODUCTION
RESEARCH
ADVISOR
MEMBERS
PUBLICATIONS
CLASS
NEWS
PHOTOS
LINKS
Laboratory news
Laboratory news
Total 103건
7 페이지
Laboratory news 목록
번호
제목
컨텐츠
조회
작성일
13
Our submission to DATE 2020, "Analysis and Solution of CNN Accuracy Reduction over Channel Loop Tiling", authored by Yesung Kang has been accepted.
2019-11-20
553
553
2019-11-20
12
Our submission to GLVLSI 2019, "Fence-Region-Aware Mixed-Height Standard Cell Legalization", authored by SangGi Do has been accepted.
2019-04-28
506
506
2019-04-28
11
Congratulations to Daeyeon Kim, Sung-Yun Lee and Minhyeok Kwon for receiving "3rd Place Award" from ISPD 2019 Contest
2019-04-25
570
570
2019-04-25
10
Congratulations to Daeyeon Kim for receiving "Best Poster Award" from KCS 2019
2019-02-19
491
491
2019-02-19
9
Our submission to ISMVL 2019, "Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm", authored by Sung-Yun Lee has been accepted.
2019-02-17
499
499
2019-02-17
8
Our submission to ISMVL 2019, "Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic", authored by Sunmean Kim has been accepted.
2019-02-17
504
504
2019-02-17
7
Congratulate 30th Anniversary of CSDL!
2019-01-10
491
491
2019-01-10
6
Congratulations to Mingyu Woo and Jaewoo Kim on filing their M.S. thesis!
2018-12-20
481
481
2018-12-20
5
Our submission to DATE 2019, "Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology", authored by Seungwon Kim has been accepted.
2018-11-20
514
514
2018-11-20
4
Our submission to DATE 2018, "Fast Chip-Package-PCB Coanalysis Methodology for Power Integrity of Multi-domain High-Speed Memory: A Case Study", authored by Seungwon Kim has been accepted.
2017-11-20
465
465
2017-11-20
3
Our submission to ASP-DAC 2018, "Optimal Static Gate Design for Synthesis of Ternary Logic Circuits", authored by Sunmean Kim has been accepted.
2017-09-20
482
482
2017-09-20
2
Our submission to ICCAD 2017, "GRASP based Metaheuristics for Layout Pattern Classification", authored by Mingyu Woo has been accepted.
2017-07-20
450
450
2017-07-20
1
Our submission to DAC 2017, "Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization", authored by Seungwon Kim has been accepted.
2016-02-20
452
452
2016-02-20
처음
1
페이지
2
페이지
3
페이지
4
페이지
5
페이지
6
페이지
열린
7
페이지
게시물 검색
검색대상
제목
내용
제목+내용
회원아이디
회원아이디(코)
글쓴이
글쓴이(코)
검색어
필수
검색
상단으로