Laboratory news
CAD & SoC Design Laboratory

Laboratory news

Total 103건 7 페이지
Laboratory news 목록
번호 컨텐츠
13
Our submission to DATE 2020, "Analysis and Solution of CNN Accuracy Reduction over Channel Loop Tiling", authored by Yesung Kang has been accepted.
2019-11-20   553
12
Our submission to GLVLSI 2019, "Fence-Region-Aware Mixed-Height Standard Cell Legalization", authored by SangGi Do has been accepted.
2019-04-28   506
11
Congratulations to Daeyeon Kim, Sung-Yun Lee and Minhyeok Kwon for receiving "3rd Place Award" from ISPD 2019 Contest
2019-04-25   570
10
Congratulations to Daeyeon Kim for receiving "Best Poster Award" from KCS 2019
2019-02-19   491
9
Our submission to ISMVL 2019, "Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm", authored by Sung-Yun Lee has been accepted.
2019-02-17   499
8
Our submission to ISMVL 2019, "Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic", authored by Sunmean Kim has been accepted.
2019-02-17   504
7
Congratulate 30th Anniversary of CSDL!
2019-01-10   491
6
Congratulations to Mingyu Woo and Jaewoo Kim on filing their M.S. thesis!
2018-12-20   481
5
Our submission to DATE 2019, "Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology", authored by Seungwon Kim has been accepted.
2018-11-20   514
4
Our submission to DATE 2018, "Fast Chip-Package-PCB Coanalysis Methodology for Power Integrity of Multi-domain High-Speed Memory: A Case Study", authored by Seungwon Kim has been accepted.
2017-11-20   465
3
Our submission to ASP-DAC 2018, "Optimal Static Gate Design for Synthesis of Ternary Logic Circuits", authored by Sunmean Kim has been accepted.
2017-09-20   482
2
Our submission to ICCAD 2017, "GRASP based Metaheuristics for Layout Pattern Classification", authored by Mingyu Woo has been accepted.
2017-07-20   450
1
Our submission to DAC 2017, "Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization", authored by Seungwon Kim has been accepted.
2016-02-20   452
게시물 검색