Our submission to ISMVL 2020, "Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction", authored by Sunmean Kim has been accepted.
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작성자 최고관리자 댓글 0건 조회 561회 작성일 20-02-21 21:53본문
Our submission to ISMVL 2020, "Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction", authored by Kiyung Kim, Sunmean Kim, Yongsu Lee, Daeyeon Kim, So-Young Kim, Seokhyeong Kang, and Byoung Hun Lee has been accepted.
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